1. Field of the Invention
The present invention relates to a method for manufacturing a capacitor for increasing an effective capacitance region of a stacked type capacitor.
2. Description of the Background Art
A DRAM (Dynamic Random Access Memory) capable of random input/output of a stored information is one of the semiconductor memory devices. DRAM is constituted by a memory cell array serving as a memory region for storing multiple pieces of information, and peripheral circuits for carrying out a prescribed input/output operation to and from this memory cell array. The memory cell array additionally includes a plurality of memory cells each corresponding to a minimum storage unit. A memory cell is basically constituted by one capacitor and one transfer gate transistor connected thereto. In operation, the memory cell determines whether a prescribed electric charge is stored in the capacitor or not, which corresponds to data "0" and "1", whereby stored information is processed.
FIG. 24 is a cross section of a conventional DRAM. This DRAM is shown, for example, in Japanese Patent Laying-Open No. 64-42161. The memory cell of DRAM shown in FIG. 24 has a so-called one transistor one capacitor type cell structure. A transfer gate transistor 10 includes a pair of n.sup.+ impurity regions 3a and 3b formed on a surface of a p type silicon substrate 1, and a gate electrode 5a with a thin gate insulating film 4 thereunder on the surface of silicon substrate 1 placed between these n.sup.+ impurity regions 3a and 3b. Gate electrode 5a is constituted by a part of a word line. A first interlayer insulating layer 30 covers around gate electrode 5a. Furthermore, a capacitor 20 includes a lower electrode (storage node) 21 connected to one n.sup.+ impurity region 3a, a dielectric layer 22 covering a surface of this lower electrode 21, and an upper electrode (cell plate) 23 covering a surface of dielectric layer 22. A bit line 7 is connected to n.sup.+ impurity region 3b through a contact hole formed in a second interlayer insulating layer 31.
Recently, as the degree of integration of a semiconductor device improves, in this type of DRAM, it becomes necessary to miniaturize each individual element. As a result, such memory cell shown in FIG. 24 is compelled to decrease a plane occupation area of capacitor 20. Therefore, mainly two methods are taken for obtaining a prescribed electrostatic capacity required for the operation of the capacitor of the memory cell.
A first method is to increase electrostatic capacity by making thin the dielectric layer 22 forming capacitor 20. For example, in a DRAM having 1M bit integration level, dielectric layer 22 is made as thin as 10 nm level in the film thickness of silicon oxide film conversion. Therefore, it is difficult to make the layer thin when its integration level further increases.
A second method is to obtain the electrostatic capacity by increasing opposing areas between electrodes 21 and 23 opposing each other with dielectric layer 22 in between. The capacitor designed by this method is referred to as a so-called stacked type capacitor. That is, it is made of a structure forming a polycrystal silicon layer having a conductivity on a surface of a diffusion layer in the semiconductor substrate, and thereafter stacking the dielectric layer and the second electrode layer on a surface of the polycrystal silicon layer. Various types of the stacked type capacitors were designed. For instance, a form of the electrode layer constituted by the polycrystal silicon was changed to a fin form, or to a cylindrically projected form.
Furthermore, as another aspect of the second method, a method of forming a roughness on the surface of the lower electrode to increase the opposing areas of the capacitor was designed. The memory cell shown in FIG. 24 has a capacitor including lower electrode 21 having such rough surface.
FIGS. 25 to 27 are cross sections showing in order, manufacturing steps (first to third steps) of the memory cell in such DRAM. Manufacturing method is described in the following in conjunction with these views.
Firstly, referring to FIG. 25, a field oxide film 2 constituted by a thick silicon oxide film is formed in a prescribed region on a surface of a p type silicon substrate 1 in accordance with LOCOS method. Thereafter, a gate oxide film 4 is formed on the surface of p type silicon substrate 1 by thermal oxidation. After depositing a polycrystal silicon layer in the whole region by CVD (Chemical Vapor Deposition) method, it is patterned to form a gate electrode 5a. A silicon oxide film is deposited in the whole region by low pressure CVD method, and thereafter a first interlayer insulating layer 30 is formed on a surface and on sides of gate electrode 5a in accordance with lithography and dry etching technologies as well known in the art. Furthermore, n.sup.+ impurity regions 3a and 3b are formed by ion implantation of impurities in p type silicon substrate by utilizing gate electrode 5a covered by interlayer insulating layer 30 as a mask.
Secondly, referring to FIG. 26, a polycrystal silicon layer 210 having the film thickness of 0.4 .mu.m is formed in accordance with low pressure CVD method utilizing a monosilane gas diluted to 20% by helium. Pressure is set at 0.8 Torr and temperature is set at 680.degree. C. The roughness in the level of 0.07 .mu.m is formed on the surface of polycrystalline silicon layer 210 manufactured by this step. Thereafter, phosphorus (P) is introduced in polycrystal silicon layer 210 by thermal diffusion method using an oxine phosphorus chloride (POCl.sub.3) as a material under the condition of the temperature of 875.degree. C. for 30 minutes. After a phosphorus glass formed in the thermal diffusion, on the surface of polycrystal silicon layer 210 is removed, thermal treatment is carried out in a nitride atmosphere at the temperature of 900.degree. C. for 20 minutes. As a result, the roughness of the surface of polycrystal silicon layer 210 expands to 0.11 .mu.m.
Referring to FIG. 27, a lower electrode 21 of a capacitor is formed by patterning polycrystal silicon layer 210 in accordance with photolithography and etching method. A thermal nitride film is formed on a surface of lower electrode 21. A silicon nitride film is formed on a surface of the thermal nitride film in accordance with CVD method. Moreover, an oxide film is formed on a surface of the silicon nitride film by thermal oxidation method. As a result, a dielectric layer 22 constituted by three layers of thermal nitride film/CVD silicon nitride film/silicon oxide film is formed.
Referring to FIG. 24, a polycrystalline silicon layer is formed on the whole region of a surface of a p type silicon substrate. It is patterned into a prescribed form, so that an upper electrode 23 of a capacitor 20 is formed. Thereafter, a second interlayer insulating layer 31 constituted by a thick oxide film is formed on the whole region. A contact hole is formed on a prescribed region of interlayer insulating layer 31, and a bit line 7 is formed in the contact hole.
The memory cell of DRAM is completed in accordance with the steps mentioned above.
Many projected parts are formed on the surface of lower electrode 21 of the capacitor formed in accordance with conventional method. FIG. 28 is an enlarged partial cross section showing the surface form of lower electrode 21. As shown in FIG. 28, there are partially narrowed regions generated in the intervals between the projected parts. When gate dielectric layer 22 is formed with the small intervals between the projections, the gap between the projections is filled up by the gate dielectric layer, resulting in not uniform film thickness of dielectric layer 22. As a result, parts which cannot provide a sufficient capacitance are generated. Under such conditions, a problem is caused. That is, an effect of increasing the capacity by increasing the opposing areas between the electrodes of the capacitors by the formation of the roughness on the surface of lower electrode 21 cannot be achieved.
As mentioned above, the gate dielectric layer is formed to have thin film thickness in order to increase capacitance of the capacitor. Therefore, when a radius of curvature of the rough parts on the surface of lower electrode 21 is small as compared with the film thickness of the gate dielectric layer, an electric field concentration is likely to be produced near such rough parts. As a result, reliability of the capacitor is decreased, because of a decrease of a breakdown voltage of the gate dielectric layer.